Display device and electronic device

ABSTRACT

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/670,531, filed Mar. 27, 2015, now allowed, which is a continuation ofU.S. application Ser. No. 12/794,939, filed Jun. 7, 2010, now U.S. Pat.No. 8,994,636, which claims the benefit of a foreign priorityapplication filed in Japan as Serial No. 2009-150617 on Jun. 25, 2009,all of which are incorporated by reference.

TECHNICAL FIELD

An embodiment of the present invention relates to a display devicedriven by an active matrix mode and an electronic device including thedisplay device.

BACKGROUND ART

A display device driven by an active matrix mode includes an elementsuch as a transistor which functions as a switch in a pixel, a drivingcircuit (a source driver) which is electrically connected to the pixeland outputs an image signal to the pixel when the switch is on, and adriving circuit (a gate driver) which controls switching of the switch.

Further, a transistor not only can function as a switch in pixels butalso can form a gate driver. Therefore, a display device including theswitches in the pixels and the gate driver which are formed using thetransistors formed using a non-single-crystal semiconductor providedover an insulating substrate is developed.

The above gate driver is provided close to a pixel portion of thedisplay device. However, the gate driver provided close to one side ofthe pixel portion results in a display portion being closer to one sidethan to the other. Thus, a display device which has gate drivers, whichare formed by dividing a gate driver, placed in both right side and leftside of the pixel portion is developed (for example, see Patent Document1).

FIG. 10 illustrates the structure of the display device disclosed inPatent Document 1. In the display device illustrated in FIG. 10, a firstgate driver 1002A and a second gate driver 1002B are provided so as toface each other with a pixel portion 1001 sandwiched therebetween. Anoutput terminal of the first gate driver 1002A is electrically connectedto an odd-numbered gate line. An output terminal of the first gatedriver 1002B is electrically connected to an even-numbered gate line.That is, the first gate driver 1002A controls an electrical connectionbetween a source driver and a pixel which is placed in an odd-numberedline in the pixel portion 1001, while the second gate driver 1002Bcontrols an electrical connection between the source driver and a pixelwhich is placed in an even-numbered line in the pixel portion 1001.

Further, the first gate driver 1002A and the second gate driver 1002Beach include a plurality of shift registers. An output terminal of thefirst shift register (SRC₁) is electrically connected to one of inputterminals of a second shift register (SRC₂) through a first gate line1003 ₁. An output terminal of the second shift register (SRC₂) iselectrically connected to one of input terminals of a third shiftregister (SRC₃) through a second gate line 1003 ₂. In a similar manner,an output terminal of a k-th shift register (SRC_(k)) is electricallyconnected to one of input terminals of a (k+1)th shift register(SRC_(k+1)) through a k-th gate line 1003 _(k). That is, a signal for anelectrical connection between a source driver and a pixel provided inone line is used as a start pulse signal of a shift register an outputterminal of which is connected to a pixel provided in the next line.

REFERENCE

[Patent Document 1] Japanese Patent No. 4163416

DISCLOSURE OF INVENTION

A gate line extending in the pixel portion has various parasiticcapacitance and parasitic resistance. In particular, an influence ofparasitic capacitances and parasitic resistances which are hold by thegate line become large as the pixel portion becomes high-quality. Asdescribed above, in the display device illustrated in FIG. 10, a startpulse signal of a shift register is inputted through a gate line.Therefore, it can be said that in the display device illustrated in FIG.10, a signal will be highly likely to be delayed or distorted signal byincrease in definition and size.

In view of the above-described problem, it is an object of an embodimentof the present invention to provide a display device which is capable offavorably displaying an image.

Further, it is an object of an embodiment of the present invention toprovide a display device whose gate driver is formed using a unipolartransistor.

Furthermore, it is an object of an embodiment of the present inventionto provide a display device including a gate driver whose circuit areais reduced.

An embodiment of the present invention is a display device. The displaydevice includes a plurality of gate lines provided so as to be parallelor approximately parallel to each other, a first gate driver which iselectrically connected to each gate line in odd-numbered rows, and asecond gate driver which is electrically connected to each gate line ineven-numbered rows. The first gate driver includes a k-th flip flopcircuit and a k-th transfer signal generation circuit (k is an oddnumber equal to or lager than 3). In the k-th flip flop circuit, anoutput terminal is electrically connected to a k-th gate line, a firstinput terminal is electrically connected to an output terminal of a(k−2)th transfer signal generation circuit, a second input terminal iselectrically connected to a clock signal line, and a third inputterminal is electrically connected to a stop pulse signal line for thek-th flip flop circuit. In the k-th transfer signal generation circuit,an output terminal is electrically connected to a first input terminalof a (k+2)th flip flop circuit, a first input terminal is electricallyconnected to the output terminal of the k-th flip flop circuit, a secondinput terminal is electrically connected to an inverted clock signalline, and a third input terminal is electrically connected to a stoppulse signal line for the k-th transfer signal generation circuit. Thesecond gate driver includes a (k+1)th flip flop circuit and a (k+1)thtransfer signal generation circuit. In the (k+1)th flip flop circuit, anoutput terminal is electrically connected to a (k+1)th gate line, afirst input terminal is electrically connected to an output terminal ofa (k−1)th transfer signal generation circuit, a second input terminal iselectrically connected to the inverted clock signal line, and a thirdinput terminal is electrically connected to a stop pulse signal line forthe (k+1)th flip flop circuit. In the (k+1)th transfer signal generationcircuit, an output terminal is electrically connected to a first inputterminal of a (k+3)th flip flop circuit, a first input terminal iselectrically connected to the output terminal of the (k+1)th flip flopcircuit, a second input terminal is electrically connected to the clocksignal line, and a third input terminal is electrically connected to astop pulse signal line for the k-th transfer signal generation circuit.

Further, a display device in which a structure of the k-th flip flopcircuit is the same as a structure of the k-th transfer signalgeneration circuit is also an embodiment of the present invention.

Note that the above stop pulse signal line is a wiring which inputs astop pulse signal to each circuit.

Specifically, an output signal of the k-th transfer signal generationcircuit can be used as a stop pulse signal for the k-th flip flopcircuit.

Alternatively, an output signal of the (k+1)th flip flop circuit can beused as a stop pulse signal for the k-th flip flop circuit.

Similarly, an output signal of the (k+2)th flip flop circuit can be usedas a stop pulse signal for the k-th transfer signal generation circuit.

Alternatively, an output signal of the (k+1)th transfer signalgeneration circuit can be used as a stop pulse signal for the k-thtransfer signal generation circuit.

In addition, an electronic device including a display device having theabove structure is also an embodiment of the present invention.

A first gate driver and a second gate driver provided in a displaydevice of an embodiment of the present invention include a transfersignal generation circuit which makes an inputted signal be outputtedwith a half clock cycle delay. Therefore, a display device which canfavorably display an image without delayed or distorted signals can beprovided.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIG. 1 illustrates a display device described in Embodiment 1;

FIG. 2 illustrates a structure of a gate driver described in Embodiment1;

FIG. 3 illustrates a timing chart of a gate driver described inEmbodiment 1;

FIG. 4 illustrates a specific example of a circuit structure describedin Embodiment 2;

FIG. 5 illustrates a timing chart of a circuit described in Embodiment2;

FIG. 6 illustrates a specific example of a circuit structure describedin Embodiment 3;

FIGS. 7A and 7B each illustrate a specific example of an invertercircuit described in Embodiment 3;

FIG. 8 illustrates a specific example of a circuit structure describedin Embodiment 4;

FIGS. 9A and 9B each illustrate a specific example of a control circuitdescribed in Embodiment 4;

FIG. 10 illustrates a structure of a gate driver shown in PatentDocument 1;

FIGS. 11A to 11F each illustrate a specific example of an electronicdevice described in Embodiment 6;

FIGS. 12A to 12D each illustrate a specific example of an electronicdevice described in Embodiment 6;

FIGS. 13A to 13D each illustrate a specific example of an electronicdevice described in Embodiment 6;

FIG. 14A illustrates a conventional circuit structure and FIG. 14Billustrates a circuit structure of this specification described inExample 1; and

FIG. 15 illustrates an output signal of a flip flop circuit of aconventional gate driver and an output signal of a flip flop circuit ofa gate driver disclosed in this specification which are described inExample 1.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments and an example of the present invention will bedescribed in detail with reference to the accompanying drawings. Notethat the present invention is not limited to the description below, andit will be easily understood by those skilled in the art that a varietyof changes and modifications can be made without departing from thespirit and scope of the present invention. Therefore, the presentinvention should not be construed as being limited to the descriptionsof the embodiments and the example below.

Embodiment 1

Embodiment 1 describes an example of a display device which is anembodiment of the present invention. Specifically, an active-matrixdisplay device including a first gate driver and a second gate driver isdescribed with reference to FIG. 1, FIG. 2, and FIG. 3.

[An Example of a Structure of a Display Device]

FIG. 1 illustrates an active-matrix display device 100. The displaydevice 100 includes a pixel portion 101, a source driver 102, a firstgate driver 103A, a second gate driver 103B, m (m is a positive integer)source lines 104 ₁ to 104 _(m) which are provided so as to be parallelor approximately parallel to each other, and n (n is a positive integer)gate lines 105 ₁ to 105 _(n) which are provided so as to be parallel orapproximately parallel to each other. Note that a pixel portion 101 isprovided in a central part of the display device 100. The source driver102 is provided close to a side of the pixel portion 101. The first gatedriver 103A and the second gate driver 103B are provided close to othersides of the pixel portion 101 and are provided so as to face each otherwith the pixel portion 101 therebetween. Further, the source driver 102is electrically connected to the pixel portion 101 through the m sourcelines 104 ₁ to 104 _(m). The first gate driver 103A is electricallyconnected to the pixel portion 101 through odd-numbered source linesamong the n gate lines 105 ₁ to 105 _(n). The second gate driver 103B iselectrically connected to the pixel portion 101 through even-numberedsource lines among then gate lines 105 ₁ to 105 _(n).

In addition, a signal (a clock signal, a start pulse signal, or thelike) is inputted from the outside to the source driver 102, the firstgate driver 103A, and the second gate driver 103B through flexibleprinted circuits 106A and 106B.

Further, the pixel portion 101 includes n×m pixels 107 ₁₁ to 107 _(nm).Note that the pixels 107 ₁₁ to 107 _(nm) are arranged inn rows and mcolumns. In addition, each of them source lines 104 ₁ to 104 _(m) iselectrically connected to n pixels which are arranged in the same row.In other words, the pixel 105 _(ij) which is arranged in the i row andthe j column (i and j are positive integers) (1≦i≦n and 1≦j≦m) iselectrically connected to the source line 104 _(j) and gate line 105_(i).

That is, the source driver 102 is electrically connected to each pixelincluded in the pixel portion 101 through the m source lines 104 ₁ to104 _(m). The first gate driver 103A is electrically connected to eachpixel arranged in odd-numbered rows in the pixel portion 101 throughodd-numbered gate lines among the n gate lines 105 ₁ to 105 _(n). Thesecond gate driver 103B is electrically connected to each pixel arrangedin even-numbered rows in the pixel portion 101 through even-numberedgate lines among the n gate lines 105 ₁ to 105 _(n).

[An Operation Example of the Display Device]

In the display device 100, the source driver 102 is a circuit whichoutputs an image signal to the pixels 107 ₁₁ to 107 _(nm) included inthe pixel portion 101. The first gate driver 103A and the second gatedriver 103B are circuits which control electrical continuity between thesource driver 102 and the pixels 107 ₁₁ to 107 _(nm).

The display device 100 displays an image in the pixel portion 101 by animage signal inputted to the n×m pixels 107 ₁₁ to 107 _(nm). A specificoperation of the display device 100 is described below.

First, the first gate driver 103A selects m pixels arranged in a firstrow (the source driver 102 and the m pixels arranged in the first roware electrically connected); then, an image signal is inputted to the mpixels 107 ₁₁ to 107 _(1m) arranged in the first row through the sourcelines 104 ₁ to 104 _(m). Next, the second gate driver 103B selects mpixels arranged in a second row; then, an image signal is inputted tothe in pixels 107 ₂₁ to 107 _(2m) arranged in the second row through thesource lines 104 ₁ to 104 _(m). After that, the first gate driver 103Aand the second gate driver 103B alternately select m pixels in each rowas in a similar manner. The display device 100 displays an image by theabove operation subsequently performed.

[A Structural Example of the Gate Driver]

FIG. 2 is a block diagram illustrating a detailed structural example ofthe first gate driver 103A and the second gate driver 103B included inthe active-matrix display device 100.

The first gate driver 103A and the second gate driver 103B each includea plurality of flip flop circuits and a plurality of transfer signalgeneration circuits which have at least three input terminals and oneoutput terminal.

In a first flip flop circuit (F₁) included in the first gate driver103A, an output terminal is electrically connected to the first gateline 105 ₁, a first input terminal is electrically connected to a firststart pulse signal (SP1) line, a second input terminal is electricallyconnected to a clock signal (CK) line, and a third input terminal iselectrically connected to a stop pulse signal (STP(F₁)) line for thefirst flip flop circuit.

Further, in a first transfer signal generation circuit (T₁) included inthe first gate driver 103A, an output terminal is electrically connectedto a first input terminal of a third flip flop circuit (F₃), a firstinput terminal is electrically connected to the output terminal of thefirst flip flop circuit (F₁), a second input terminal is electricallyconnected to an inverted clock signal (CKB) line, and a third inputterminal is electrically connected to a stop pulse signal (STP(T₁)) linefor the first transfer signal generation circuit.

In a second flip flop circuit (F₂) included in the second gate driver103B, an output terminal is electrically connected to the second gateline 105 ₂, a first input terminal is electrically connected to a secondstart pulse signal (SP2) line, a second input terminal is electricallyconnected to the inverted clock signal (CKB) line, and a third inputterminal is electrically connected to a stop pulse signal (STP(F₂)) linefor the second flip flop circuit.

Further, in a second transfer signal generation circuit (T₂) included inthe second gate driver 103B, an output terminal is electricallyconnected to a first input terminal of a fourth flip flop circuit (notshown), a first input terminal is electrically connected to the outputterminal of the second flip flop circuit (F₂), a second input terminalis electrically connected to the clock signal (CK) line, and a thirdinput terminal is electrically connected to the stop pulse signal(STP(T₂)) line for the second transfer signal generation circuit.

In a k-th (k is an odd number equal to or larger than three) flip flopcircuit (F_(k)) included in the first gate driver 103A, an outputterminal is electrically connected to a k-th gate line 105 _(k), a firstinput terminal is electrically connected to an output terminal of a(k−2)th transfer signal generation circuit (T_(k−2)), a second inputterminal is electrically connected to the clock signal (CK) line, and athird input terminal is electrically connected to a stop pulse signal(STP(F_(k))) line for a k-th flip flop circuit.

Further, in a k-th transfer signal generation circuit (T_(k)) includedin the first gate driver 103A, an output terminal is electricallyconnected to a (k+2)th flip flop circuit (F_(k+2)), a first inputterminal is electrically connected to the output terminal of the k-thflip flop circuit (F_(k)), a second input terminal is electricallyconnected to the inverted clock signal (CKB) line, and a third inputterminal is electrically connected to a stop pulse signal (STP(T_(k)))line for a k-th transfer signal generation circuit.

In a (k+1)th flip flop circuit (F_(k+1)) included in the second gatedriver 103B, an output terminal is electrically connected to a (k+1)thgate line 105 _(k+1), a first input terminal is electrically connectedto an output terminal of a (k−1)th transfer signal generation circuit(T_(k−1)), a second input terminal is electrically connected to theinverted clock signal (CKB) line, and a third input terminal iselectrically connected to a stop pulse signal (STP(F_(k+1))) line for a(k+1)th flip flop circuit.

Further, in a (k+1)th transfer signal generation circuit (T_(k+1))included in the second gate driver 103B, an output terminal iselectrically connected to a (k+3)th flip flop circuit (F_(k+3)), a firstinput terminal is electrically connected to an output terminal of the(k+1)th flip flop circuit (F_(k+1)), a second input terminal iselectrically connected to the clock signal (CK) line, and a third inputterminal is electrically connected to a stop pulse signal (STP(T_(k+1)))line for a (k+1)th transfer signal generation circuit.

The above plurality of flip flop circuits and plurality of transfersignal generation circuits included in the first gate driver 103A andthe above plurality of flip flop circuits and plurality of transfersignal generation circuits included in the second gate driver 103B havesimilarities and differences in an electrical connection relationship. Aspecific difference is described below.

First, a difference in an electrical connection relationship between theflip flop circuit and the transfer signal generation circuit included inthe first gate driver, and the flip flop circuit and the transfer signalgeneration circuit included in the second gate driver is describedbelow.

In the first gate driver 103A, a second input terminal of a flip flopcircuit is electrically connected to the clock signal (CK) line, and asecond input terminal of a transfer signal generation circuit iselectrically connected to the inverted clock signal (CKB) line. On theother hand, in the second gate driver 103B, a second input terminal of aflip flop circuit is electrically connected to the inverted clock signal(CKB) line, and a second input terminal of a transfer signal generationcircuit is electrically connected to the clock signal (CK) line.

Next, the difference in an electrical connection relationship of theflip flop circuit and the transfer signal generation circuit isdescribed below.

As the output terminal of the first flip flop circuit (F₁) is connectedto the first gate line 105 ₁, an output terminal of a flip flop circuitis electrically connected to a gate line which is provided in the samerow. On the other hand, as the output terminal of the first transfersignal generation circuit (T₁) is electrically connected to the firstinput terminal of the third flip flop circuit (F₃), an output terminalof a transfer signal generation circuit is electrically connected to afirst input terminal of a flip flop circuit provided in the next stage.Note that first input terminals of the first flip flop circuit (F₁) andthe second flip flop circuit (F₂), which do not have transfer signalcircuits in the previous stages, are electrically connected to the firststart pulse signal (SP1) line and the second start pulse signal (SP2)line, respectively.

In addition, each of third input terminals of all the flip flop circuitsand all the transfer signal generation circuits is electricallyconnected to corresponding stop pulse signal (STP) lines.

[An Example of Operation of the Gate Driver]

FIG. 3 is a timing chart. Note that, in FIG. 3, a clock signal (CK), aninverted clock signal (CKB), a first start pulse signal (SP1), a secondstart pulse signal (SP2), an output signal of the first flip flopcircuit (F₁OUT) to an output signal of the fourth flip flop circuit(F₄OUT), and an output signal of the first transfer signal generationcircuit (T₁OUT) to an output signal of the fourth transfer signalgeneration circuit (T₄OUT) are illustrated. Note that a clock signal(CK) is a signal which oscillates between a high (hereinafter, referredto as H) level and a low (hereinafter, referred to as L) level at aconstant frequency. An inverted clock signal (CKB) is a signal whoselevel is inverted from the level of the clock signal.

In a period T1, the first start pulse signal (SP1) goes to an H level,and an H level signal is inputted to the first input terminal of thefirst flip flop circuit (F₁).

In a period T2, a second start pulse signal (SP2) goes to the H level,and an H level signal is inputted to the first input terminal of thesecond flip flop circuit (F₂). In addition, an H level signal isoutputted from the first flip flop circuit (F₁). Note that an H levelsignal which is outputted from the first flip flop circuit (F₁) isinputted through the first gate line 105 ₁ to each of the pixels 107 ₁₁to 107 _(1m) arranged in the first row in the pixel portion 101.Accordingly, each of the pixels 107 ₁₁ to 107 _(1m) arranged in thefirst row and the source driver 102 are electrically connected, so thatan image signal is inputted from the source driver 102 to each of thepixels 107 ₁₁ to 107 _(1m) arranged in the first row. Further, an Hlevel signal outputted from the first flip flop circuit (F₁) is inputtedto the first input terminal of the first transfer signal generationcircuit (T₁).

In a period T3, an H level signal is outputted from the second flip flopcircuit (F₂). As when the output signal of the first flip flop circuit(F₁) is in the H level, an H level signal which is outputted from thesecond flip flop circuit (F₂) is inputted through the first gate line105 ₂ to each of the pixels 107 ₂₁ to 107 _(2m) arranged in the secondrow in the pixel portion 101. Accordingly, each of the pixels 107 ₂₁ to107 _(2m) arranged in the second row and the source driver 102 areelectrically connected, so that an image signal is inputted from thesource driver 102 to each of the pixels 107 ₂₁ to 107 _(2m) arranged inthe second row. In addition, an H level signal is outputted from thefirst transfer signal generation circuit (T₁) and inputted to the firstinput terminal of the third flip flop circuit (F₃).

From a period T4, the above-described operations are repeated. That is,an H level signal is sequentially outputted from the next flip flopcircuits from the third flip flop circuit (F₃), so that an image signalis inputted to a plurality of arranged pixels in each row.

The display device described in this embodiment is an active-matrixdisplay device including a first gate driver and a second gate driver.Further, the first gate driver and the second gate driver each include aplurality of flip flop circuits and a plurality of transfer signalgeneration circuits. Both the flip flop circuit and the transfer signalgeneration circuit are circuits which output a signal inputted to afirst input terminal with a half clock cycle delay. In addition, anoutput terminal of the transfer signal generation circuit is directlyconnected to a first input terminal of the flip flop circuit in the nextstage. Therefore, delay and distortion of the signal which is inputtedfrom the transfer signal generation circuit to the flip flop circuit canbe reduced.

Note that, in this embodiment, an example of a display device includingone source driver and two gate drivers are described. However, anembodiment of the present invention is not limited to this structure.For example, the following structures are also one of embodiments of thepresent invention: a structure where a display device only includes twogate drivers and an image signal is inputted from the outside, astructure where a display device includes two source drivers and twogate drivers and an image signal is inputted from the two sourcedrivers, and a structure where each pixel is electrically connected to agate driver through two gate lines.

Embodiment 2

In Embodiment 2, a specific example of a circuit which can be applied tothe flip flop circuit and the transfer signal generation circuitdescribed in Embodiment 1 is described with reference to FIG. 4 and FIG.5. Specifically, an example of forming a flip flop circuit and atransfer signal generation circuit using transistors is illustrated.Note that since a source terminal and a drain terminal of a transistorchange depending on the structure, the operating condition, and the likeof the transistor, it is difficult to define which is a source terminalor a drain terminal. Therefore, one of a source terminal and a drainterminal is referred to as a first terminal and the other thereof isreferred to as a second terminal for distinction, hereinafter.

[An Example of a Circuit Structure]

FIG. 4 is a diagram illustrating an example of a circuit which can beapplied to the k-th flip flop circuit (F_(k)) and the k-th transfersignal generation circuit (T_(k)) included in the first gate driver 103Adescribed in Embodiment 1. Note that a k-th flip flop circuit (F_(k))described in Embodiment 2 includes a first transistor 401 to a fourthtransistor 404 and a k-th transfer signal generation circuit (T_(k))includes a fifth transistor 405 to an eighth transistor 408. Inaddition, in Embodiment 2, an output signal (T_(k)OUT) of the k-thtransfer signal generation circuit is used as a stop pulse signal(STP(F_(k))) for the k-th flip flop circuit. An output signal(F_(k+2)OUT) of a (k+2)th flip flop circuit is used as a stop pulsesignal (STP(T_(k))) for the k-th transfer signal generation circuit.

In the first transistor 401, a gate terminal and a first terminal areelectrically connected to an output terminal of a (k−2)th transfersignal generation circuit (not shown).

A gate terminal of the second transistor 402 is electrically connectedto an output terminal of the k-th transfer signal generation circuit(T_(k)), a first terminal of the second transistor 402 is electricallyconnected to a ground potential (VSS) line, and a second terminal of thesecond transistor 402 is electrically connected to a second terminal ofthe first transistor 401.

A gate terminal of the third transistor 403 is electrically connected tothe second terminal of the first transistor 401 and the second terminalof the second transistor 402, a first terminal of the third transistor403 is electrically connected to a clock signal (CK) line, and a secondterminal of the third transistor 403 is electrically connected to afirst input terminal of the k-th transfer signal generation circuit(T_(k)).

A gate terminal of the fourth transistor 404 is electrically connectedto the output terminal of the k-th transfer signal generation circuit(T_(k)), a first terminal of the fourth transistor 404 is electricallyconnected to the ground potential (VSS) line, and a second terminal ofthe fourth transistor 404 is electrically connected to the first inputterminal of the k-th transfer signal generation circuit (T_(k)) and thesecond terminal of the third transistor 403.

A gate terminal and a first terminal of the fifth transistor 405 areelectrically connected to an output terminal of the k-th flip flopcircuit (F_(k)).

A gate terminal of the sixth transistor 406 is electrically connected toan output terminal of the (k+2)th flip flop circuit (not shown), a firstterminal of the sixth transistor 406 is electrically connected to theground potential (VSS) line, and a second terminal of the sixthtransistor 406 is electrically connected to a second terminal of thefifth transistor 405.

A gate terminal of the seventh transistor 407 is electrically connectedto the second terminal of the fifth transistor 405 and the secondterminal of the sixth transistor 406, a first terminal of the seventhtransistor 407 is electrically connected to an inverted clock signal(CKB) line, a second terminal of the seventh transistor 407 iselectrically connected to a third input terminal of the k-th flip flopcircuit (F_(k)) and a first input terminal of the (k+2)th flip flopcircuit (not shown).

A gate terminal of the eighth transistor 408 is electrically connectedto the output terminal of the (k+2)th flip flop circuit (not shown), afirst terminal of the eighth transistor 408 is electrically connected tothe ground potential (VSS) line, and a second terminal of the eighthtransistor 408 is electrically connected to the third input terminal ofthe k-th flip flop circuit (F_(k)), the first input terminal of the(k+2)th flip flop circuit (not shown), and the second terminal of theseventh transistor 407.

As illustrated in FIG. 4, the same circuit structure can be applied tothe k-th flip flop circuit (F_(k)) and the k-th transfer signalgeneration circuit (T_(k)). Note that points described below arepreferably considered when a circuit is designed.

The k-th flip flop circuit (F_(k)) is a circuit for driving a k-th gateline. The k-th transfer signal generation circuit (T_(k)) is a circuitfor driving the (k+2)th flip flop circuit. The k-th gate line hasvarious parasitic capacitance and parasitic resistance as describedabove. Therefore, the load of the k-th flip flop circuit (F_(k)) isheavier than the load of the k-th transfer signal generation circuit(T_(k)). That is, when the above circuit is designed, the currentdriving capability of the first transistor 401 is preferably higher thanthe current driving capability of the fifth transistor 405. For example,the channel width of the first transistor 401 may be larger than thechannel width of the fifth transistor 405. For the same reason, it ispreferable that the current driving capability of the second transistor402 be higher than the current driving capability of the sixthtransistor 406, the current driving capability of the third transistor403 be higher than the current driving capability of the seventhtransistor 407, and the current driving capability of the fourthtransistor 404 be higher than the current driving capability of theeighth transistor 408. For example, the current driving capability canbe higher by making a ratio of the channel width to the channel length(the channel width/the channel length (W/L)) larger.

Further, the third transistor 403 which directly contributes to drivingof the k-th gate line preferably has the highest current drivingcapability among the first transistor 401 to the fourth transistor 404included in the k-th flip flop circuit (F_(k)). Similarly, the seventhtransistor 407 which directly contributes to a driving of the (k+2)thflip flop circuit preferably has the highest current driving capabilityamong the fifth transistor 405 to the eighth transistor 408 included inthe k-th transfer signal generation circuit (T_(k)).

In addition, the circuit structure illustrated in FIG. 4 can be appliedto the first flip flop circuit (F₁) and the first transfer signalgeneration circuit (T₁) included in the first gate driver 103A. Notethat, in the first flip flop circuit (F₁), what is different from thestructure illustrated in FIG. 4 is that the gate terminal and the firstterminal of the first transistor 401 are electrically connected to thefirst start pulse signal (SP1) line.

Further, the circuit structure illustrated in FIG. 4 can be applied tothe (k+1)th flip flop circuit (F_(k+1)) and the (k+1)th transfer signalgeneration circuit (T_(k+1)) included in the second gate driver 103B.Note that, in the (k+1)th flip flop circuit (F_(k+1)) and the (k+1)thtransfer signal generation circuit (T_(k+1)), what is different from thestructure illustrated in FIG. 4 is that the first terminal of the thirdtransistor 403 is electrically connected to the inverted clock signal(CKB) line and that the first terminal of the seventh transistor 407 iselectrically connected to the clock signal (CK) line.

Furthermore, the circuit structure illustrated in FIG. 4 can be appliedto the second flip flop circuit (F₂) and the second transfer signalgeneration circuit (T₂) included in the second gate driver 103B. Notethat, in the second flip flop circuit (F₂) and the second transfersignal generation circuit (T₂), the difference from the structure inFIG. 4 is as follows: the gate terminal and the first terminal of thefirst transistor 401 are electrically connected to the second startpulse signal (SP2) line, the first terminal of the transistor 403 iselectrically connected to the inverted clock signal (CKB) line, and thefirst terminal of the seventh transistor 407 is electrically connectedto the clock signal (CK) line.

Note that, in Embodiment 2, an output signal (F_(k+2)OUT) of the (k+2)thflip flop circuit is used as the stop pulse (STP(T_(k))) for the k-thtransfer signal generation circuit. Therefore, for a plurality of pixelsarranged in n rows, an (n+1)th flip flop circuit needs to be provided asa dummy circuit in the first gate driver 103A, and an (n+2)th flip flopcircuit needs to be provided as a dummy circuit in the second gatedriver 103B. Note that as the dummy circuit, a flip flop circuit whichonly supplies a stop pulse signal for the transfer signal generationcircuit and does not drive a gate line can be used. Alternatively, byproviding a wiring (a dummy gate line) which does not contribute todisplay together with the dummy circuit, a flip flop circuit whichsupplies a stop pulse signal for a transfer signal generation circuitand drives the wiring can be used as the dummy circuit.

[An Example of a Circuit Operation]

FIG. 5 is a timing chart of input signals and output signals of the k-thflip flop circuit (F_(k)) and the k-th transfer signal generationcircuit (T_(k)) illustrated in FIG. 4. Operations of the k-th flip flopcircuit (F_(k)) and the k-th transfer signal generation circuit (T_(k))are described below.

In a period t1, an output signal (T_(k−2)OUT) of the (k−2)th transfersignal generation circuit goes to an H level. Thus, the first transistor401 which is diode-connected is turned on, and a potential of the gateterminal of the third transistor 403 is increased to the H level.Therefore, a clock signal (CK) which is in an L level in the period t1is outputted as an output signal (F_(k)OUT) of the k-th flip flopcircuit.

In a period t2, the output signal (T_(k−2)OUT) of the (k−2)th transfersignal generation circuit goes to the L level and the clock signal (CK)goes to the H level. Thus, the first transistor 401 which isdiode-connected is turned off; accordingly, a potential of the gateterminal of the third transistor 403 at a floating state is raised by anH level signal inputted to the first terminal of the third transistor403 (a bootstrap operation) and further increased. Further, the thirdtransistor 403 remains ON, and an H level signal is outputted as theoutput signal (F_(k)OUT) of the k-th flip flop circuit (F_(k)). This Hlevel signal is inputted to the gate terminal and the first terminal ofthe fifth transistor 405. Thus, the fifth transistor 405 which isdiode-connected is turned on; accordingly, a potential of the gateterminal of the seventh transistor 407 is increased up to the H level.Therefore, an inverted clock signal (CKB) which is in the L level in theperiod t2 is outputted as an output signal (T_(k)OUT) of the k-thtransfer signal generation circuit (T_(k)).

In a period t3, the clock signal goes to the L level and the invertedclock signal (CKB) goes to the H level. Thus, the fifth transistor 405which is diode-connected is turned off; accordingly, a potential of thegate terminal of the seventh transistor 407 at a floating state israised by an H level signal inputted to the first terminal of theseventh transistor 407 (a bootstrap operation) and further increased.Further, the seventh transistor 407 remains ON, and an H level signal isoutputted to the output signal (T_(k)OUT) of the k-th transfer signalgeneration circuit (T_(k)). This H level signal is inputted to the gateterminals of the second transistor 402 and the fourth transistor 404.Thus, the second transistor 402 is turned on, and a potential of thegate terminal of the third transistor 403 goes to the L level. Thereforethe third transistor 403 is turned off. In addition, since the fourthtransistor 404 is turned on, the L level signal is outputted as theoutput signal (F_(k)OUT) of the k-th flip flop circuit (F_(k)).

In a period t4, the output signal (F_(k+2)OUT) of the (k+2)th flip flopcircuit goes to the H level. Thus, the sixth transistor 406 is turned onand a potential of the gate terminal of the seventh transistor 407 goesto the L level. Therefore, the seventh transistor 407 is turned off.Further, since the eighth transistor 408 is also turned on, the L levelsignal is outputted as the output signal (T_(k)OUT) of the k-th transfersignal generation circuit (T_(k)).

Note that a circuit operation of the following circuits is the same asthe circuit operation of the above-described k-th flip flop circuit(F_(k)) and k-th transfer signal generation circuit (T_(k)): the firstflip flop circuit and the first transfer signal generation circuit, the(k+1)th flip flop circuit and the (k+1)th transfer signal generationcircuit, and the second flip flop circuit and the second transfer signalgeneration circuit.

Modification Example

In Embodiment 2, an output signal of the k-th transfer signal generationcircuit (T_(k)) and an output signal of the (k+2)th flip flop circuit(F_(k+2)) are used as a stop pulse signal (STP(F_(k))) for the k-th flipflop circuit and a stop pulse signal (STP(T_(k))) for the k-th transfersignal generation circuit, respectively. However, the structure ofEmbodiment 2 is not limited thereto.

For example, an output signal of the (k+1)th flip flop circuit (F_(k+1))and an output signal of the (k+1)th transfer signal generation circuit(T_(k+1)) can be used as a stop pulse signal (STP(F_(k))) for the k-thflip flop circuit and a stop pulse signal (STP(T_(k))) for the k-thtransfer signal generation circuit, respectively. In this ease, the stoppulse signal (STP(F_(k))) for the k-th flip flop circuit and the stoppulse signal (STP(T_(k))) for the k-th transfer signal generationcircuit are delayed or distorted signals as compared with those in theabove structure. However, since an output signal of the k-th flip flopcircuit (F_(k)) and an output signal of the k-th transfer signalgeneration circuit (T_(k)) in the period go into the L level, a delayedor distorted signal does not provide a serious problem.

Embodiment 3

In Embodiment 3, a specific example of a circuit which can be applied tothe flip flop circuit and the transfer signal generation circuitdescribed in Embodiment 1, which is different from a specific example inEmbodiment 2, is described with reference to FIG. 6 and FIGS. 7A and 7B.

[An Example of a Circuit Structure]

FIG. 6 illustrates an example of a circuit which can be applied to thek-th flip flop circuit (F_(k)) and the k-th transfer signal generationcircuit (T_(k)) included in the first gate driver 103A described inEmbodiment 1. In Embodiment 3, a k-th flip flop circuit (F_(k)) includesa first transistor 601 to a fifth transistor 605 and an inverter circuit600, and a k-th transfer signal generation circuit (T_(k)) includes asixth transistor 606 to an eighth transistor 608. Note that, in otherwords, the circuit illustrated in FIG. 6 is made as follows: theinverter circuit 600 and the fifth transistor 605 are added to the k-thflip flop circuit (F_(k)) illustrated in FIG. 4 and the eighthtransistor 408 is eliminated from the k-th transfer signal generationcircuit (T_(k)) illustrated in FIG. 4.

The electrical connection relationship between the first transistor 601,the second transistor 602, and the third transistor 603 is the same asthat in the circuit illustrated in FIG. 4. Therefore, the description inEmbodiment 2 applies here.

An input terminal of the inverter circuit 600 is electrically connectedto a second terminal of the first transistor 601, a second terminal ofthe second transistor 602, and a gate terminal of the third transistor603.

A gate terminal of the fourth transistor 604 is electrically connectedto an output terminal of the inverter circuit 600, a first terminal ofthe fourth transistor 604 is electrically connected to a groundpotential (VSS) line, and a second terminal of the fourth transistor 604is electrically connected to a second terminal of the third transistor603 and a first input terminal of the k-th transfer signal generationcircuit (T_(k)).

A gate terminal of the fifth transistor 605 is electrically connected tothe output terminal of the inverter circuit 600, a first terminal of thefifth transistor 605 is electrically connected to the ground potential(VSS) line, and a second terminal of the fifth transistor 605 iselectrically connected to the second terminal of the first transistor601, the second terminal of the second transistor 602, the gate terminalof the third transistor 603, and the input terminal of the invertercircuit 600.

The k-th transfer signal generation circuit (T_(k)) illustrated in FIG.6 is a circuit in which the eighth transistor 408 is eliminated from thek-th transfer signal generation circuit (T_(k)) illustrated in FIG. 4.The electrical connection relationship between the other transistors isthe same as that in the circuit illustrated in FIG. 4. Therefore, thedescription in Embodiment 2 applies here.

Note that the circuit illustrated in FIG. 6 needs to be designed asdescribed below.

The circuit illustrated in FIG. 6 needs to be designed so that an Hlevel signal is surely inputted to the input terminal of the invertercircuit 600 when an H level signal is inputted into the k-th flip flopcircuit (F_(k)) (the first transistor 601 which is diode-connected).More specifically, the current driving capability of the firsttransistor 601 needs to be higher than the current driving capability ofthe fifth transistor 605. For example, the channel width of the firsttransistor 601 needs to be larger than the channel width of the fifthtransistor 605.

Further, in the period t4 illustrated in FIG. 5, an output signal(T_(k)OUT) of the k-th transfer signal generation circuit goes to an Llevel. More specifically, the current driving capability of the eighthtransistor 608 needs to be higher than the current driving capability ofthe seventh transistor 607. Thus, the output signal (T_(k)OUT) of thek-th transfer signal generation circuit can be reduced to an L levelwhich is equal to an inverted clock signal (CKB) level in the period t4before the following operation: an H level signal is inputted to a gateterminal of the seventh transistor 607, the seventh transistor 607 isturned on, a ground potential (VSS) is inputted to a gate terminal ofthe eighth transistor 608, and then, the eighth transistor 608 is turnedoff.

Further, the description in Embodiment 2 is preferably taken intoconsideration when the circuit illustrated in FIG. 6 is designed.

That is, it is preferable that the current driving capability of thefirst transistor 601 be higher than the current driving capability ofthe sixth transistor 606, the current driving capability of the secondtransistor 602 be higher than the current driving capability of theseventh transistor 607, and the current driving capability of the thirdtransistor 603 be higher than the current driving capability of theeighth transistor 608.

Furthermore, it is preferable that the third transistor 603 have thehighest current driving capability among the first transistor 601 to thefifth transistor 605 included in the k-th flip flop circuit (F_(k)). Inaddition, it is preferable that the eighth transistor 608 have thehighest current driving capability among the sixth transistor 606 to theeighth transistor 608 included in the k-th transfer signal generationcircuit (T_(k)).

Note that the circuit in FIG. 6 can also be applied to a (k+1)th flipflop circuit, a (k+1)th transfer signal generation circuit, and the likethough FIG. 6 illustrates only the k-th flip flop circuit (F_(k)) andthe k-th transfer signal generation circuit (T_(k)). Note that asdescribed in Embodiment 2, part of the electrical connectionrelationship of terminals is different. The description of Embodiment 2applies to a specific difference of the connection relationship.

FIGS. 7A and 7B are diagrams illustrating specific examples of a circuitwhich can be applied to the inverter circuit 600 illustrated in FIG. 6.Note that in FIGS. 7A and 7B, a wiring denoted by “IN” is an inputwiring and a wiring denoted by “OUT” is an output wiring.

An inverter circuit 600A illustrated in FIG. 7A includes a transistor701A which is diode-connected and a transistor 702A.

A gate terminal and a first terminal of the transistor 701A areelectrically connected to a power supply (VDD) line, and a secondterminal of the transistor 701A is electrically connected to an outputterminal of the inverter circuit 600A.

A gate terminal of the transistor 702A is electrically connected to aninput terminal of the inverter circuit 600A, a first terminal of thetransistor 702A is electrically connected to a ground potential (VSS)line, and a second terminal of the transistor 702A is electricallyconnected to an output terminal of the inverter circuit 600A and thesecond terminal of the transistor 701A.

Since the inverter circuit 600A illustrated in FIG. 7A is formed usingthe two transistors 701A and 702B, an increase in the circuit area canbe minimized.

Note that, in the case where the inverter circuit 600A illustrated inFIG. 7A is applied to the inverter circuit 600 in FIG. 6, the circuitneeds to be designed so that an output signal is in the L level when thetransistor 702A is ON. More specifically, the current driving capabilityof the transistor 702A needs to be higher than the current drivingcapability of the transistor 701A. For example, the channel length ofthe transistor 702A needs to be smaller than the channel length of thetransistor 701A, or the channel width of the transistor 702A needs to belarger than the channel width of the transistor 701A.

The inverter circuit 600B illustrated in FIG. 7B includes a transistor701B which is diode-connected, a transistor 702B, a transistor 703B, anda transistor 704B.

A gate terminal and a first terminal of the transistor 701B areelectrically connected to the power supply (VDD) line.

A gate terminal of the transistor 702B is electrically connected to aninput terminal of the inverter circuit 600B, a first terminal of thetransistor 702B is electrically connected to the ground potential (VSS)line, and a second terminal of the transistor 702B is electricallyconnected to a second terminal of the transistor 701B.

A gate terminal of the transistor 703B is electrically connected to thesecond terminal of the transistor 701B and the second terminal of thetransistor 702B, a first terminal of the transistor 703B is electricallyconnected to the power supply potential (VDD) line, and a secondterminal of the transistor 703B is electrically connected to an outputterminal of the inverter circuit 600B.

A gate terminal of the transistor 704B is electrically connected to theinput terminal of the inverter circuit 600B, a first terminal of thetransistor 704B is electrically connected to the ground potential (VSS)line, and a second terminal of the transistor 704B is electricallyconnected to the output terminal of the inverter circuit 600B and thesecond terminal of the transistor 703B.

In the inverter circuit 600B illustrated in FIG. 7B, the transistor 701Bwhich is diode-connected is not directly connected to the outputterminal of the inverter circuit 600B. Therefore, an output signal canbe prevented from being decreased from the power supply potential (VDD)or increased from the ground potential (VSS).

Note that, in the case where the inverter circuit 600B illustrated inFIG. 7B is applied to the inverter circuit 600 illustrated in FIG. 6,the circuit needs to be designed so that the transistor 703B is turnedoff when the transistor 702B is ON. More specifically, the currentdriving capability of the transistor 702B needs to be higher than thecurrent driving capability of the transistor 701B. For example, thechannel length of the transistor 702B needs to be smaller than thechannel length of the transistor 701B, or the channel width of thetransistor 702B needs to be larger than the channel width of thetransistor 701B.

[Difference from the Circuit Described in Embodiment 2]

The k-th flip flop circuit (F_(k)) illustrated in FIG. 6 includes theinverter circuit 600 and the fifth transistor 605 whose gate terminal iselectrically connected to the output terminal of the inverter circuit600, first terminal is electrically connected to the ground potential(VSS) line, and second terminal is electrically connected to the inputterminal of the inverter circuit 600. Thus, the fifth transistor 605which is electrically connected to the inverter circuit 600 is always ONonce the fifth transistor 605 is turned on. When the fifth transistor605 is ON, a potential of the gate terminal of the third transistor 603is maintained at the ground potential (VSS). Therefore, even when noisesenter the gate terminal of the third transistor 603, the thirdtransistor 603 is not turned on. That is, an image or a picture of adisplay device is not defected and high performance of the displaydevice can be realized.

Since the k-th transfer signal generation circuit (T_(k)) illustrated inFIG. 6 is formed using the three transistors 606 to 608, the circuitarea can be reduced.

Modification Example

In Embodiment 3, an example of the flip flop circuit formed using thefive transistors 601 to 605 and the inverter circuit 600, and thetransfer signal generation circuit formed using the three transistors606 to 608 is described. However, an embodiment is not limited to such astructure. For example, both the k-th flip flop circuit (F_(k)) and thek-th transfer signal generation circuit (T_(k)) may have the samestructure as the k-th flip flop circuit (F_(k)) or the k-th transfersignal generation circuit (T_(k)) illustrated in FIG. 6. Further, theflip flop circuit and the transfer signal generation circuit can beformed by combination of the circuit in Embodiment 2 (FIG. 4) and thecircuit in Embodiment 3 (FIG. 6).

Furthermore, in Embodiment 3, the output signal of the k-th transfersignal generation circuit (T_(k)) and the output signal of the (k+2)thflip flop circuit (F_(k+2)) are applied to the stop pulse signal(STP(F_(k))) for the k-th flip flop circuit and the stop pulse signal(STP(T_(k))) for the k-th transfer signal generation circuit,respectively. However, a structure in Embodiment 3 is not limited tosuch a structure.

Embodiment 4

In Embodiment 4, a specific example of a circuit which can be applied tothe flip flop circuit and the transfer signal generation circuitdescribed in Embodiment 1, which is different from a specific example inEmbodiments 2 and 3, is described with reference to FIG. 8 and FIGS. 9Aand 9B.

[An Example of a Circuit Structure]

FIG. 8 illustrates an example of a circuit which can be applied to thek-th flip flop circuit (F_(k)) and the k-th transfer signal generationcircuit (T_(k)) included in the first gate driver 103A which isdescribed in Embodiment 1. In Embodiment 4, a k-th flip flop circuit(F_(k)) includes a first transistor 801 to a fifth transistor 805 and ancontrol circuit 800, and a k-th transfer signal generation circuit(T_(k)) includes a sixth transistor 806 to a ninth transistor 809. Notethat, in other words, the circuit illustrated in FIG. 8 is made asfollows: the control circuit 800 and the fifth transistor 805 are addedto the circuit illustrated in FIG. 4 and a first terminal of the sixthtransistor 806 (corresponding to the fifth transistor 405 in FIG. 4) iselectrically connected to a power supply potential (VDD) line not to agate terminal of the transistor 806.

The electrical connection relationship between the first transistor 801,the second transistor 802, and the third transistor 803 is the same asthat in the circuit illustrated in FIG. 4 and FIG. 6. Therefore, thedescription in Embodiment 2 applies here.

A first Input terminal of the control circuit 800 is electricallyconnected to a second terminal of the first transistor 801, a secondterminal of the second transistor 802, and a gate terminal of the thirdtransistor 803, and a second input terminal of the control circuit 800is electrically connected to the clock signal (CK) line.

A gate terminal of the fourth transistor 804 is electrically connectedto an output terminal of the control circuit 800, a first terminal ofthe fourth transistor 804 is electrically connected to the groundpotential (VSS) line, and a second terminal of the fourth transistor 804is electrically connected to a second terminal of the third transistor803 and a first input terminal of the k-th transfer signal generationcircuit (T_(k)).

A gate terminal of the fifth transistor 805 is electrically connected tothe output terminal of the control circuit 800, a first terminal of thefifth transistor 805 is electrically connected to the ground potential(VSS) line, a second terminal of the fifth transistor 805 iselectrically connected to the second terminal of the first transistor801, the second terminal of the second transistor 802, the gate terminalof the third transistor 803, and a first input terminal of the controlcircuit 800.

A gate terminal of the sixth transistor 806 is electrically connected toan output terminal of the k-th flip flop circuit (F_(k)), and a firstterminal of the sixth transistor 806 is electrically connected to thepower supply potential (VDD) line.

The electrical connection relationship between the seventh transistor807, the eighth transistor 808, and the ninth transistor 809 is the sameas that of the sixth transistor 606, the seventh transistor 607, and theeighth transistor 608 illustrated in FIG. 6. Therefore, the descriptionin Embodiment 2 applies here.

Note that the circuit illustrated in FIG. 8 needs to be designed asdescribed below.

The circuit illustrated in FIG. 8 needs to be designed so that an Hlevel signal is surely inputted to the input terminal of the controlcircuit 800 when an H level signal is inputted into the k-th flip flopcircuit (F_(k)) (the first transistor 801 which is diode-connected).More specifically, the current driving capability of the firsttransistor 801 needs to be higher than the current driving capability ofthe fifth transistor 805. For example, the channel width of the firsttransistor 801 needs to be larger than the channel width of the fifthtransistor 805.

Further, the description in Embodiment 2 is preferably taken intoconsideration when a circuit illustrated in FIG. 8 is designed.

That is, it is preferable that the current driving capability of thefirst transistor 801 be higher than the current driving capability ofthe sixth transistor 806, the current driving capability of the secondtransistor 802 be higher than the current driving capability of theseventh transistor 807, the current driving capability of the thirdtransistor 803 be higher than the current driving capability of theeighth transistor 808, and the current driving capability of the fourthtransistor 804 be higher than the current driving capability of theninth transistor 809.

Furthermore, it is preferable that the third transistor 803 have thehighest current driving capability among the first transistor 801 to thefifth transistor 805 included in the k-th flip flop circuit (F_(k)). Inaddition, it is preferable that the eighth transistor 808 have thehighest current driving capability among the sixth transistor 806 to theninth transistor 809 included in the k-th transfer signal generationcircuit (T_(k)).

The circuit in FIG. 8 can be applied to the (k+1)th flip flop circuit(F_(k+1)), the (k+1)th transfer signal generation circuit (T_(k+1)), andthe like though FIG. 8 illustrates only the k-th flip flop circuit(F_(k)) and the k-th transfer signal generation circuit (T_(k)). Notethat as described in Embodiment 2, part of the electrical connectionrelationship of terminals is different. The description of Embodiment 2applies to a specific difference of the connection relationship.

FIGS. 9A and 9B are diagrams illustrating specific examples of a circuitwhich can be applied to the control circuit 800 illustrated in FIG. 8.In FIGS. 9A and 9B, a wiring denoted by “IN” is a first input wiring, awiring denoted by “CK” is a second input wiring which is electricallyconnected to a clock signal (CK) line, and a wiring denoted by “OUT” isan output wiring.

The control circuit 800A illustrated in FIG. 9A includes a capacitorelement 901A and a transistor 902A.

One of terminals of the capacitor element 901A is electrically connectedto the clock signal (CK) line and the other terminal is electricallyconnected to an output terminal of the control circuit 800A.

A gate terminal of the transistor 902A is electrically connected to afirst input terminal of the control circuit 800A, a first terminal ofthe transistor 902A is electrically connected to a ground potential(VSS) line, and a second terminal of the transistor 902A is electricallyconnected to the output terminal of the control circuit 800A and theother terminal of the capacitor element 901A.

After the period t3 in FIG. 5, the L level signal is inputted to thefirst input terminal of the control circuit 800A and the transistor 902Ais turned off. Accordingly, an output signal of the control circuit 800Abecomes in a floating state. Therefore, as an output signal of thecontrol circuit 800A, a signal which is tuned to the clock signal (CK)is outputted.

Note that in the case where the control circuit 800A illustrated in FIG.9A is applied to the control circuit 800 in FIG. 8, the control circuit800A needs to be designed so that when transition from the period t2 tothe period t3 occurs, its output terminal goes into a floating stateafter a potential of one of the terminals of the capacitor element 901Agoes to an L level.

The control circuit 800B illustrated in FIG. 9B includes a transistor901B which is diode-connected, a transistor 902B, a transistor 903B, anda transistor 904B.

A gate terminal and a first terminal of the transistor 901B areelectrically connected to a clock signal (CK) line.

A gate terminal of the transistor 902B is electrically connected to afirst input terminal of the control circuit 800B, a first terminal ofthe transistor 902B is electrically connected to a ground potential(VSS) line, and a second terminal of the transistor 902B is electricallyconnected to a second terminal of the transistor 901B.

A gate terminal of the transistor 903B is electrically connected to thesecond terminal of the transistor 901B and the second terminal of thetransistor 902B, a first terminal of the transistor 903B is electricallyconnected to the clock signal (CK) line, and a second terminal of thetransistor 903B is electrically connected to an output terminal of thecontrol circuit 800B.

A gate terminal of the transistor 904B is electrically connected to theinput terminal of the control circuit 800B, a first terminal of thetransistor 904B is electrically connected to the ground potential (VSS)line, and a second terminal of the transistor 904B is electricallyconnected to the output tenithial of the control circuit 800B and thesecond terminal of the transistor 903B.

Note that, in the case where the control circuit 800B illustrated inFIG. 9B is applied to the control circuit 800 illustrated in FIG. 8, thecircuit needs to be designed so that the transistor 903B is turned offwhen the transistor 902B is ON. More specifically, the current drivingcapability of the transistor 902B needs to be higher than the currentdriving capability of the transistor 901B. For example, the channellength of the transistor 902B needs to be smaller than the channellength of the transistor 901B, or the channel width of the transistor902B needs to be larger than the channel width of the transistor 901B.

[Difference from the Circuit Described in Embodiments 2 and 3]

The control circuits 800A and 800B illustrated in FIGS. 9A and 9B outputa clock signal (CK) or a signal tuned to the clock signal (CK).Therefore, even when noises enter the gate terminal of the thirdtransistor 803, the noises can be eliminated when the fourth transistor804 and the fifth transistor 805 are turned on. Further, the fourthtransistor 804 and the fifth transistor 805 are not always ON, wherebydeterioration of the fourth transistor 804 and the fifth transistor 805can be suppressed. That is, an image of a display device is notdefected, so that performance and reliability of the display device canbe increased.

Modification Example

In Embodiment 4, an example of the flip flop circuit formed using thefive transistors 801 to 805 and the control circuit 800 and the transfersignal generation circuit formed using the four transistors 806 to 809are described. However, an embodiment is not limited to such astructure. For example, both the k-th flip flop circuit (F_(k)) and thek-th transfer signal generation circuit (T_(k)) may have the samestructure as the k-th flip flop circuit (F_(k)) or the k-th transfersignal generation circuit (T_(k)) illustrated in FIG. 8. Further, theflip flop circuit and the transfer signal generation circuit can beformed by combination of the circuit in Embodiment 2 (FIG. 4) orEmbodiment 3 (FIG. 6) and the circuit in Embodiment 4 (FIG. 8).

Furthermore, in Embodiment 4, the output signal of the k-th transfersignal generation circuit (T_(k)) and the output signal of the (k+2)thflip flop circuit (F_(k+2)) are applied to the stop pulse signal(STP(F_(k))) for the k-th flip flop circuit and the stop pulse signal(STP(T_(k))) for the k-th transfer signal generation circuit,respectively. However, a structure in Embodiment 4 is not limited tosuch a structure.

Embodiment 5

In Embodiment 5, a specific example of a transistor included in the flipflop circuit and the transfer signal generation circuit described inEmbodiments 2 to 4 is described.

As the transistor, transistors which are formed using various materialsand structures can be used. That is, there are no limitations on thetype of transistors used. For example, a thin film transistor (TFT)including a non-single-crystal semiconductor film typified by a filmmade of amorphous silicon, polycrystalline silicon, microcrystalline(also referred to as microcrystal, nanocrystal, or semi-amorphous)silicon, or the like can be used.

The use of the thin film transistor for manufacturing a display devicehas various advantages. Since a thin film transistor can be formed attemperature lower than that at which a transistor using single crystalsilicon is formed, reduction in manufacturing cost of a display deviceor increase in size of a manufacturing device can be realized. Further,since a thin film transistor can be manufactured at low temperature, thethin film transistor can be formed over a substrate with low heatresistance. Therefore, the transistor can be formed using alight-transmitting substrate with low heat resistance. In addition,since the thickness of the thin film transistor is thin, part of a filmforming the transistor can transmit light. Accordingly, the apertureratio can be increased.

In addition, a MOS transistor, a junction transistor, a bipolartransistor, or the like can be used as the transistor. Note that thesize of a transistor can be reduced by the use of a MOS transistor asthe transistor. Alternatively, the use of a bipolar transistor as thetransistor allows a large amount of current to flow. Therefore, ahigh-speed operation is possible. Note that a MOS transistor and abipolar transistor may be formed over one substrate. Thus, reduction inpower consumption, reduction in size, a high-speed operation, and thelike can be realized.

Note that by using a catalyst (e.g., nickel) for forming polycrystallinesilicon, crystallinity can be further improved, and a thin filmtransistor having excellent electric characteristics can be formed.Accordingly, a gate driver circuit, a source driver circuit, and asignal processing circuit (e.g., a signal generation circuit, a gammacorrection circuit, or a DA converter circuit) can be formed over thesame substrate.

Further, by using a catalyst (e.g., nickel) for forming microcrystallinesilicon, crystallinity can be further improved, and a transistor havingexcellent electric characteristics can be formed. At this time,crystallinity can be improved by just performing heat treatment withoutperforming laser light irradiation. As a result, a gate driver circuitand part of a source driver circuit (e.g., an analog switch) can beformed over the same substrate. Note that in the case where laserirradiation for crystallization is not performed, unevenness incrystallinity of silicon can be suppressed. Thus, an image with improvedimage quality can be displayed.

Note that polycrystalline silicon or microcrystalline silicon can beformed without use of a catalyst (e.g., nickel).

Further, it is preferable that the entire silicon be improved incrystallinity but Embodiment 5 is not limited thereto. Only part ofsilicon may be improved in crystallinity. Selective increase incrystallinity can be achieved by selective laser irradiation or thelike. For example, a region of a gate driver, a source driver, or thelike may be irradiated with laser light. As a result, crystallinity ofsilicon can be improved only in a region in which a circuit needs tooperate at high speed. Since a pixel portion does not need to be drivenat high speed, a pixel circuit can be driven without a serious problemeven when crystallinity is not improved; thus, a region where thecrystallinity is improved is reduced and manufacturing process becomesshorter. Therefore, throughput is improved, so that manufacturing costof a display device can be reduced.

In addition, the transistor is not limited to a transistor formed usingsilicon. As the transistor, a transistor formed using a compoundsemiconductor such as silicon germanium and gallium arsenide, or anoxide semiconductor such as zinc oxide and zinc oxide including indiumand gallium can be employed. Further, a thin film transistor including athin film formed of such a compound semiconductors or oxidesemiconductor can be employed. Since the thin film transistor can bemanufactured at low temperature, a transistor can be formed at roomtemperature, for example. Accordingly, the transistor can be formeddirectly on a substrate with low heat resistance, such as a plasticsubstrate or a film substrate. Note that such a compound semiconductoror an oxide semiconductor can be used not only for a channel portion ofthe transistor but also for other applications. For example, such acompound semiconductor or an oxide semiconductor can be used for awiring, a resistor, a pixel electrode, a light-transmitting electrode,or the like. Since such an element can be deposited or formed at thesame time as the transistor, manufacturing cost of a display device canbe reduced.

Further, a transistor including an organic semiconductor or a carbonnanotube can be used as the transistor. Accordingly, transistors can beformed over a substrate which can be bent. A display device using such asubstrate can resist shock.

In addition, a manufacturing method of the transistor is not limited. Asthe manufacturing method, a photolithography method, an inkjet method, aprinting method, or the like can be employed. Note that, since a mask(reticle) is not used during manufacture in an inkjet method and aprinting method, a layout of a transistor can be changed with ease.Furthermore, since the transistor can be formed without use of a resist,material cost is reduced and the number of steps can be reduced. Inaddition, since a film can be formed where needed, a material is notwasted. Therefore, cost can be reduced.

Alternatively, as the transistor, a multi-gate transistor having two ormore gate terminals can be used. With the multi-gate structure, astructure where a plurality of transistors are connected in series isobtained because channel regions are connected in series. Therefore,with the multi-gate structure, off-current of a transistor is reducedand the withstand voltage of the transistor can be increased (thereliability can be improved).

As the transistor, a transistor with a structure where gate terminalsare formed above and below a channel region can also be used. Byproviding gate terminals above and below a channel region, a structurewhere a plurality of transistors are connected in parallel is obtained.That is, the channel region is increased. Thus, the amount of currentcan be increased. Further, by employing the structure where gateterminals are formed above and below the channel region, a depletionlayer is easily formed; thus, an S value can be improved.

In addition, a transistor with the following structure can be used asthe transistor: a structure where a gate terminal is formed above achannel region, a structure where a gate terminal is formed below achannel region, a forward staggered structure, an inverted staggeredstructure, a structure where a channel region is divided into aplurality of regions, a structure where channel regions are connected inparallel or in series, or the like.

Further alternatively, as the transistor, a transistor with a structurewhere a source terminal or a drain terminal overlaps with a channelregion (or part of it) can be used. When the structure where the sourceterminal or the drain terminal overlaps with the channel region (or partof it) is used, electric charges can be prevented from being accumulatedin part of the channel region, which would result in an unstableoperation.

Furthermore, a structure in which an LDD region is provided can beapplied to the transistor. By providing the LDD region, off-current of atransistor is reduced and the withstand voltage of the transistor can beincreased (the reliability can be improved). In addition, by providingthe LDD region, drain-source current is not changed very much even whendrain-source voltage is changed when the transistor operates in thesaturation region, so that a flat slope of voltage-currentcharacteristics can be obtained.

Note that the transistor can be formed using various substrates. Thatis, the type of a substrate is not limited to a certain type. As thesubstrate, a semiconductor substrate (e.g., a single crystal substrateor a silicon substrate), an SOI substrate, a glass substrate, a quartzsubstrate, a plastic substrate, a metal substrate, a stainless steelsubstrate, a substrate including stainless steel foil, a tungstensubstrate, a substrate including tungsten foil, a flexible substrate, anattachment film, paper including a fibrous material, a base materialfilm, or the like can be used, for example. As an example of a glasssubstrate, a barium borosilicate glass substrate, an aluminoborosilicateglass substrate, a soda lime glass substrate, or the like can be given.For a flexible substrate, a flexible synthetic resin such as plasticstypified by polyethylene terephthalate (PET), polyethylene naphthalate(PEN), and polyether sulfone (PES), or acrylic can be used, for example.Examples of an attachment film are an attachment film formed usingpolypropylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride,and the like. Examples of a base film are a base film formed usingpolyester, polyamide, polyimide, inorganic vapor deposition film, paper,and the like. In particular, when a transistor is formed using asemiconductor substrate, a single crystal substrate, an SOI substrate,or the like, a transistor with few variations in characteristics, size,shape, or the like, high current supply capability, and a small size canbe formed. By forming a circuit using such transistors, powerconsumption of the circuit can be reduced or the circuit can be highlyintegrated.

Alternatively, the transistor may be formed using one substrate, andthen, the transistor may be transferred to and provided over anothersubstrate. Example of a substrate to which a transistor is transferredare, in addition to the above-described substrate over which thetransistor can be formed, a paper substrate, a cellophane substrate, astone substrate, a wood substrate, a cloth substrate (including anatural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g.,nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate,cupra, rayon, or regenerated polyester), or the like), a leathersubstrate, a rubber substrate, and the like. By using such a substrate,transistors with excellent properties or transistors with low powerconsumption and a device with high durability, high heat resistance,light weight, or thin thickness can be formed.

Embodiment 6

In Embodiment 6, examples of electronic devices including the displaydevice described in Embodiment 1 are described with reference to FIGS.11A to 11F, FIGS. 12A to 12D, and FIGS. 13A to 13D.

FIGS. 11A to 11F and FIGS. 12A to 12D illustrate electronic devicesincluding the display device described in Embodiment 1. These electronicdevices can include a housing 5000, a display portion 5001, a speaker5003, an LED lamp 5004, operation keys 5005 (including a power switch oran operation switch), a connection terminal 5006, a sensor 5007 (asensor having a function of measuring force, displacement, position,speed, acceleration, angular velocity, rotational frequency, distance,visible light, liquid, magnetism, temperature, chemical substance,sound, time, hardness, electric field, current, voltage, electric power,radiation, flow rate, humidity, gradient, oscillation, odor, or infraredray), a microphone 5008, and the like. In these electronic devices, thedisplay device described in Embodiment 1 is incorporated in the displayportion 5001.

FIG. 11A illustrates a mobile computer, which can include a switch 5009,an infrared port 5010, and the like in addition to the above objects.FIG. 11B illustrates a portable image regenerating device provided witha memory medium (e.g., a DVD regenerating device), which can include asecond display portion 5002, a memory medium reading portion 5011, andthe like in addition to the above objects. FIG. 1 IC illustrates aprojector, which can include a light source 5033, a projection lens5034, and the like in addition to the above objects. FIG. 11Dillustrates a portable game machine, which can include the memory mediumreading portion 5011 and the like in addition to the above objects. FIG.11E illustrates a television receiver, which can include a tuner, animage processing portion, and the like in addition to the above objects.FIG. 11F illustrates a portable television receiver, which can include acharger 5017 capable of transmitting and receiving signals and the likein addition to the above objects. FIG. 12A illustrates a display, whichcan include a support base 5018 and the like in addition to the aboveobjects. FIG. 12B illustrates a camera, which can include an externalconnecting port 5019, a shutter button 5015, an image receiving portion5016, and the like in addition to the above objects. FIG. 12Cillustrates a computer, which can include a pointing device 5020, theexternal connecting port 5019, a reader/writer 5021, and the like inaddition to the above objects. FIG. 12D illustrates a mobile phone,which can include an antenna, a tuner of one-segment (1seg digital TVbroadcasts) partial reception service for mobile phones and mobileterminals, and the like in addition to the above objects.

The electronic devices illustrated in FIGS. 11A to 11F and FIGS. 12A to12D can have a variety of functions, for example, a function ofdisplaying a lot of information (e.g., a still image, a moving image,and a text image) on a display portion; a touch panel function; afunction of displaying a calendar, date, time, and the like; a functionof controlling processing with a lot of software (programs); a wirelesscommunication function; a function of being connected to a variety ofcomputer networks with a wireless communication function; a function oftransmitting and receiving a lot of data with a wireless communicationfunction; and a function of reading a program or data stored in a memorymedium and displaying the program or data on a display portion. Further,the electronic device including a plurality of display portions can havea function of displaying image information mainly on one display portionwhile displaying text information on another display portion, a functionof displaying a three-dimensional image by displaying images whereparallax is considered on a plurality of display portions, or the like.Furthermore, the electronic device including an image receiving portioncan have a function of photographing a still image, a function ofphotographing a moving image, a function of automatically or manuallycorrecting a photographed image, a function of storing a photographedimage in a memory medium (an external memory medium or a memory mediumincorporated in the camera), a function of displaying a photographedimage on the display portion, or the like. Note that functions which canbe provided for the electronic devices illustrated in FIGS. 11A to 11Fand FIGS. 12A to 12D are not limited thereto, and the electronic devicescan have a variety of functions.

An example of the electronic devices incorporated in a building isdescribed with reference to FIGS. 13A and 13B.

FIG. 13A illustrates an example of an electronic device incorporated ina building. The electronic device includes a housing 5022, a displayportion 5023, a speaker 5025, and the like. The electronic device can beoperated with a remote controller 5024. The electronic device isincorporated in the building as a wall-hanging type and can be providedwithout requiring a large space.

FIG. 13B illustrates an example of an electronic device incorporated ina building. The electronic device includes a display portion 5026 and isprovided near a bathtub 5027, so that a person in the bathtub can viewthe display portion 5026.

Note that although in Embodiment 6, the wall and the bathtub are givenas examples of the building, Embodiment 6 is not limited to them. Thedisplay panel can be provided in a variety of building.

Next, examples in which an electronic device is incorporated in a movingobject are described with reference to FIGS. 13C and 13D.

FIG. 13C illustrates an example in which an electronic deviceincorporated in a car. The electronic device includes a display portion5028 is incorporated in a car body 5029. The electronic device candisplay information related to the operation of the car or informationinputted from inside or outside of the car on demand. Note that theelectronic device may have a navigation function.

FIG. 13D illustrates an example of an electronic device provided in apassenger airplane. More specifically, FIG. 13D illustrates anapplication of the electronic device which is provided on a ceiling 5030above a seat of the passenger airplane. The electronic device isincorporated in the ceiling 5030 with a hinge portion 5032, and apassenger can view the display portion 5031 by stretching of the hingeportion 5032. The electronic device has a function of displayinginformation by the operation of the passenger.

Note that although bodies of a car and an airplane are described asexamples of moving objects in Embodiment 6, Embodiment 6 is not limitedto them. The electronic devices can be provided for a variety of objectssuch as two-wheeled vehicles, four-wheeled vehicles (including cars,buses, and the like), trains (including monorails, railroads, and thelike), and vessels.

The electronic devices described in this embodiment are characterized byhaving a display portion for displaying some sort of information and byhaving the display device described in Embodiment 1 incorporated in thedisplay portion.

Example 1

In Example 1, suppression effect of a distorted or delayed signal in agate driver including a transfer signal generation circuit is verifiedwith a circuit simulation by comparison with a conventional example.

FIGS. 14A and 14B respectively illustrate circuit simulation models of aconventional gate driver and a gate driver in this specification. FIG.14A illustrates a structure of the conventional gate driver in which anoutput signal of each flip flop circuit is used as a start pulse signalof the next flip flop circuit. HU 14B illustrates a structure of thegate driver in this specification in which a transfer signal generationcircuit is provided between flip flop circuits.

In Example 1, output signals of the flip flop circuits in the case wherethe circuit illustrated in FIG. 4 was used as the flip flop circuits andthe transfer signal generation circuit were calculated by a circuitsimulation. Note that calculation software which was used was PSpice.Further, it is assumed that the threshold voltage of the transistorincluded in a flip flop circuit and a transfer signal generation circuitwas 8 V and the field effect mobility thereof was 0.5 cm²/Vs. Inaddition, it is assumed that a parasitic capacitance of 100 pF wasformed in each gate line. Further, it is assumed that the voltageamplitude of a clock signal was 30 V (a potential of an H level was 30 Vand a potential of an L level was 0 V), a ground voltage was 0 V, and aclock frequency was 41.7 kHz (a period was 24 μs).

FIG. 15 illustrates the output signal of the flip flop circuitscalculated by a circuit simulation. As FIG. 15 illustrates, it wasconfirmed that delayed and distorted signals are reduced in the gatedriver in this specification.

This application is based on Japanese Patent Application serial no.2009-150617 filed with Japan Patent Office on Jun. 25, 2009, the entirecontents of which are hereby incorporated by reference.

REFERENCE NUMERALS

-   -   100: display device; 101: pixel portion; 102: source driver;        103A: first gate driver; 103B: second gate driver; 104 ₁: source        line; 104 _(m): source line; 105 ₁:gate line; 105 ₂:gate line;        105 ₃:gate line; 105 _(n):gate line; 106A: flexible printed        circuit; 106B: flexible printed circuit; 107 ₁₁: pixel; 107        _(nm): pixel; 401: transistor; 402: transistor; 403: transistor;        404: transistor; 405: transistor; 406: transistor; 407:        transistor; 408: transistor; 600: inverter circuit; 600A:        inverter circuit; 600B: inverter circuit; 601: transistor; 602:        transistor; 603: transistor; 604: transistor; 605: transistor;        606: transistor; 607: transistor; 608: transistor; 701A:        transistor; 701B: transistor; 702A: transistor; 702B:        transistor; 703B: transistor; 704B: transistor; 800: control        circuit; 800A: control circuit; 800B: control circuit; 801:        transistor; 802: transistor; 803: transistor; 804: transistor;        805: transistor; 806: transistor; 807: transistor; 808:        transistor; 809: transistor; 901A: capacitor element; 901A:        transistor; 901B: transistor; 902A: transistor; 902B:        transistor; 903B: transistor; 904B: transistor; 1001: pixel        portion; 1002A: first gate driver; 1002B: second gate driver;        1003 ₁: gate line; 1003 ₂: gate line; 1003 _(k): gate line;        5000: housing; 5001: display portion; 5002: second display        portion; 5003: speaker; 5004: LED lamp; 5005: operation key;        5006: connection terminal; 5007: sensor; 5008: microphone; 5009:        switch; 5010: infrared port; 5011: memory medium reading        portion; 5015: shutter button; 5016: image receiving portion;        5017: charger; 5018: support base; 5019: external connecting        port; 5020: pointing device; 5021: reader/writer; 5022: housing;        5023: display portion; 5024: remote controller; 5025: speaker;        5026: display portion; 5027: bathtub; 5028: display portion;        5029: car body; 5030: ceiling; 5031: display portion; 5032:        hinge portion; 5033: light source; 5034: projection lens.

1. (canceled)
 2. A display device comprising: a pixel portion comprisinga plurality of gate lines; and a first gate driver adjacent to the pixelportion, the first gate driver comprising: a first transistorelectrically connected to a k-th gate line among the plurality of gatelines and configured to output a signal to select the k-th gate line; asecond transistor electrically connected to a (k+2)-th gate line amongthe plurality of gate lines and configured to output a signal to selectthe (k+2)-th gate line; and a circuit comprising a third transistorconfigured to turn on the second transistor in accordance with thesignal output from the first transistor, wherein a current drivingcapability of the first transistor is higher than a current drivingcapability of the third transistor.
 3. The display device according toclaim 2, wherein a current driving capability of the second transistoris larger than the current driving capability of the third transistor.4. The display device according to claim 2, wherein a channel width ofthe first transistor is larger than a channel width of the thirdtransistor.
 5. The display device according to claim 2, wherein achannel width of the second transistor is larger than the channel widthof the third transistor.
 6. The display device according to claim 2,wherein a ratio of a channel width to a channel length of the firsttransistor is larger than a ratio of a channel width to a channel lengthof the third transistor.
 7. The display device according to claim 2,wherein a ratio of a channel width to a channel length of the secondtransistor is larger than the ratio of the channel width to the channellength of the third transistor.
 8. The display device according to claim2, wherein the first transistor is included in a first flip flop circuitand the second transistor is included in a second flip flop circuit. 9.The display device according to claim 2, wherein the circuit is atransfer signal generation circuit.
 10. The display device according toclaim 2, wherein the k-th gate line is electrically connected to thecircuit.
 11. The display device according to claim 2, wherein the firsttransistor and the second transistor are electrically connected to aclock signal line.
 12. The display device according to claim 2, furthercomprising a second gate driver adjacent to the pixel portion, whereinthe pixel portion is located between the first gate driver and thesecond gate driver.
 13. The display device according to claim 12,wherein the second gate driver comprises: a fourth transistorelectrically connected to a (k+1)-th gate line among the plurality ofgate lines and configured to output a signal to select the (k+1)-th gateline; and a fifth transistor electrically connected to a (k+3)-th gateline among the plurality of gate lines and configured to output a signalto select the (k+3)-th gate line.
 14. A display device comprising: apixel portion comprising a plurality of gate lines; and a first gatedriver adjacent to the pixel portion, the first gate driver comprising:a first circuit comprising a first transistor, a second transistor, athird transistor, and a fourth transistor; and a second circuitcomprising a fifth transistor, a sixth transistor, a seventh transistor,and an eighth transistor, wherein: one of a source and a drain of thefirst transistor is directly connected to a first wiring; the other ofthe source and the drain of the first transistor is directly connectedto a second wiring configured to be supplied with a first clock signal;one of a source and a drain of the second transistor is directlyconnected to the first wiring; the other of the source and the drain ofthe second transistor is directly connected to a third wiring; one of asource and a drain of the third transistor is directly connected to agate of the first transistor; a gate of the third transistor is directlyconnected to a fourth wiring; one of a source and a drain of the fourthtransistor is directly connected to the gate of the first transistor;the other of the source and the drain of the fourth transistor isdirectly connected to the third wiring; a gate of the fourth transistoris directly connected to a fifth wiring; one of a source and a drain ofthe fifth transistor is directly connected to the fifth wiring; theother of the source and the drain of the fifth transistor is directlyconnected to a sixth wiring configured to be supplied with a secondclock signal; one of a source and a drain of the sixth transistor isdirectly connected to the fifth wiring; the other of the source and thedrain of the sixth transistor is directly connected to the third wiring;one of a source and a drain of the seventh transistor is directlyconnected to a gate of the fifth transistor; a gate of the seventhtransistor is directly connected to the first wiring; one of a sourceand a drain of the eighth transistor is directly connected to the gateof the fifth transistor; the other of the source and the drain of theeighth transistor is directly connected to the third wiring; a gate ofthe eighth transistor is directly connected to a seventh wiring; thesecond circuit is configured to output a first stop pulse signal to thegate of the fourth transistor through the fifth wiring; the seventhwiring is configured to be supplied with a second stop pulse signal; anda ratio of a channel width to a channel length of the fourth transistoris larger than a ratio of a channel width to a channel length of theeighth transistor.
 15. The display device according to claim 14, whereinthe first circuit is configured to output a signal to at least one ofthe plurality of gate lines and the second circuit is configured not tooutput a signal to any of the plurality of gate lines.
 16. A displaydevice comprising: a pixel portion comprising a plurality of gate lines;and a first gate driver adjacent to the pixel portion, the first gatedriver comprising: a first circuit comprising a first transistor, asecond transistor, a third transistor, a fourth transistor, a fifthtransistor, a sixth transistor, a seventh transistor, an eighthtransistor, and a ninth transistor; and a second circuit comprising atenth transistor, an eleventh transistor, and twelfth transistor,wherein: one of a source and a drain of the first transistor is directlyconnected to a first wiring; the other of the source and the drain ofthe first transistor is directly connected to a second wiring configuredto be supplied with a first clock signal; one of a source and a drain ofthe second transistor is directly connected to the first wiring; theother of the source and the drain of the second transistor is directlyconnected to a third wiring; one of a source and a drain of the thirdtransistor is directly connected to a gate of the first transistor; agate of the third transistor is directly connected to a fourth wiring;one of a source and a drain of the fourth transistor is directlyconnected to the gate of the first transistor; the other of the sourceand the drain of the fourth transistor is directly connected to thethird wiring; one of a source and a drain of the fifth transistor isdirectly connected to the first transistor; the other of the source andthe drain f the fifth transistor is directly connected to the thirdwiring; a gate of the fifth transistor is directly connected to a fifthwiring; one of a source and a drain of the sixth transistor is directlyconnected to a gate of the second transistor and a gate of the fourthtransistor; the other of the source and the drain of the sixthtransistor is directly connected to a sixth wiring; one of a source anda drain of the seventh transistor is directly connected to the gate ofthe second transistor and the gate of the fourth transistor; the otherof the source and the drain of the seventh transistor is directlyconnected to the third wiring; a gate of the seventh transistor isdirectly connected to the gate of the first transistor; one of a sourceand a drain of the eighth transistor is directly connected to a gate ofthe sixth transistor; the other of the source and the drain of theeighth transistor is directly connected to the sixth wiring; a gate ofthe eighth transistor is directly connected to the sixth wiring; one ofa source and a drain of the ninth transistor is directly connected tothe gate of the sixth transistor; the other of the source and the drainof the ninth transistor is directly connected to the third wiring; agate of the ninth transistor is directly connected to the gate of thefirst transistor; one of a source and a drain of the tenth transistor isdirectly connected to the fifth wiring; the other of the source and thedrain of the tenth transistor is directly connected to a seventh wiringconfigured to be supplied with a second clock signal; one of a sourceand a drain of the eleventh transistor is directly connected to a gateof the tenth transistor; a gate of the eleventh transistor is directlyconnected to the first wiring; one of a source and a drain of thetwelfth transistor is directly connected to the gate of the tenthtransistor; the other of the source and the drain of the twelfthtransistor is directly connected to the third wiring; a gate of thetwelfth transistor is directly connected to an eighth wiring; the secondcircuit is configured to output a first stop pulse signal to the gate ofthe fifth transistor through the fifth wiring; the eighth wiring isconfigured to be supplied with a second stop pulse signal; and a ratioof a channel width to a channel length of the fifth transistor is largerthan a ratio of a channel width to a channel length of the twelfthtransistor.
 17. The display device according to claim 16, wherein thefirst circuit is configured to output a signal to at least one of theplurality of gate lines and the second circuit is configured not tooutput a signal to any of the plurality of gate lines.